The invention lies in the integrated technology field. More specifically, the invention relates to a lithography method for patterning layers during the fabrication of integrated circuits, and to a mask suitable for use in the lithography process.
Lithography methods, which are based in particular on photolithography processes, are used for fabricating integrated circuits, in particular for fabricating interconnects for the wiring of integrated circuits.
Interconnects of this type are usually incorporated in insulator layers seated directly, or with the interposition of a metal layer, on a substrate containing the integrated circuits. Substrates of this type are usually formed of silicon layers, and the insulator layers are usually formed of oxide layers, preferably silicon oxides.
The fabrication of the interconnects in the insulator layer involves making contact holes and trenches running in one plane or in a plurality of planes, etching processes, in particular plasma etching processes, preferably being used for this purpose.
In order to make these trenches and contact holes in the insulator layer, a resist mask having a hole pattern corresponding to the trenches and/or to the contact holes is applied to the insulator layer. It is customary also for a plurality of resist masks to be applied one after the other in a multistage process, in order to make contact holes and/or trenches in a plurality of planes of the insulator layer.
The individual trenches and contact holes are etched in with predetermined depths through the corresponding openings in the resist masks. The resist masks are then removed from the insulator layer. Finally, metal is deposited into the trenches and/or contact holes in order to fabricate the interconnects.
The fabrication of resist masks on the insulator layers is effected with known photolithography processes. In that case, first of all a radiation-sensitive resist layer is applied to the insulator layer. The emplacement of templates or the like results in the resist layer being exposed to radiation, in particular light radiation, at predetermined locations. Afterward, either only the exposed or only the unexposed regions of the resist layer are removed in a suitable developer. A so-called positive resist is present in the first case, and a negative resist in the second case. The resist layer with the hole pattern produced in this way then forms the resist mask for the subsequent etching processes.
During the exposure process, the radiation, in particular light beams, should be imaged as accurately as possible onto the surface of the resist layer in accordance with a predetermined hole pattern. The object is thereby to obtain a maximum resolution, which is synonymous with obtaining the most abrupt transition possible between exposed and unexposed locations in the photoresist layer.
The exposure is thereby effected in such a way that radiation is emitted by a radiation source and focused via an objective onto an image plane in which the resist layer is situated. In the image plane, individual substrates with the resist layers applied thereon are positioned by means of a stepper in the beam path of the beams emitted by the radiation source.
In the course of exposure, the radiation is guided through a mask, wherein it is possible for a specific exposure pattern to be predetermined by the structure of the mask. The mask is usually designed as a binary mask, for example in the form of a chromium mask. Such chromium masks have an alternating structure of transparent regions, preferably formed by a glass layer, and non-transparent layers, formed by the chromium layers.
In order to increase the contrast between exposed and unexposed regions on the resist layer, a phase mask is used instead of a chromium mask.
Such a phase mask may be designed, in particular, as a halftone phase mask. In the case of such halftone phase masks, the opaque layer is replaced by a semitransparent layer having a transmission typically of 6%, whose layer thicknesses are designed such that the radiation that passes through experiences a phase swing of 180xc2x0.
Furthermore, the phase mask may also be structured as an alternating phase mask. Such an alternating phase mask has adjacent transparent regions which are separated by a chromium layer in each case and each have phases shifted by 180xc2x0. This means that the radiation which passes through one transparent region has a phase offset of 180xc2x0 relative to the radiation which is guided through the adjacent transparent region.
Irrespective of the choice of different masks, the minimum feature sizes which can be produced using prior art photolithography methods are limited by the wavelengths of the predetermined radiation. In conventional photolithography methods, lasers are usually used as radiation sources, the wavelengths of which preferably lie in the visible region. Smaller feature sizes can be produced for example by using lasers which emit radiation in a wavelength range of about 200 nm. Examples of such radiation sources are argon fluoride lasers which emit radiation at wavelengths of about 193 nm.
The object of the invention is to provide a lithography method and a mask suitable therefor which overcome the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and which enable the production of structures in photosensitive layers with the smallest possible feature sizes.
With the above and other objects in view there is provided, in accordance with the invention, a lithography method for patterning layers during the fabrication of integrated circuits, which comprises:
emitting radiation in an extreme ultraviolet range from a radiation source;
guiding the radiation via a mask; and
guiding the radiation from the mask and exposing a photosensitive layer of material to the radiation.
In accordance with an added feature of the invention, the radiation emitted from the radiation source lies in a wavelength range of 11 nmxe2x89xa6xcexxe2x89xa614 nm.
In accordance with an additional feature of the invention, a xenon plasma source is used as the radiation source.
In the case of the lithography method according to the invention, for the purpose of patterning layers during the fabrication of integrated circuits, photosensitive layers are exposed with radiation whose wavelength lies in the ultraviolet region. On a mask there are a plurality of feature sizes which are exposed with the same wavelength. In this case, the wavelengths used preferably lie in the range from 11 nm to 14 nm.
The method according to the invention enables the minimum feature sizes which are produced on the photosensitive layers to be considerably reduced. The minimum feature size which can be fabricated using a lithography method is defined by the following relationship:
x=k1xc2x7xcex/NA
where xcex is the wavelength of the radiation used in the exposure and NA is the numerical aperture of the imaging system used. The factor k1 is dependent on the design of the respective mask used. For binary masks, the factor k1 lies in the range between 0.5 and 0.7. If a halftone phase mask is used, the factor k1 typically lies in the range from 0.38 to 0.55. The best results are obtained with alternating phase masks. In this case, the factor k1 lies in the range from 0.2 to 0.38.
For the exposure, the invention uses radiation in the extreme ultraviolet region, whose wavelengths are about one order of magnitude shorter than in the case of known photolithography methods. The optical imaging system then preferably comprises mirror systems. Although the apertures used in this case are distinctly smaller than the apertures used in conventional light optics, this is overcompensated by the reduction in the wavelength, so that a distinctly improved resolution is obtained compared with conventional light optical systems.
With the above and other objects in view there is also provided, in accordance with the invention, a mask assembly for performing the afore-mentioned lithography method. The mask assembly is formed with a plurality of layers, the layers having a feature sizes matched to a wavelength of the radiation emitted by the radiation source and lying in the extreme ultraviolet range.
The mask assembly according to the invention may not only be formed as a binary mask but also as a phase mask, in which case the phase mask may be designed as a halftone phase mask or else as an alternating phase mask.
In the latter case, the masks according to the invention are each expediently constructed in such a way that they have a thin, transparent silicon layer as carrier layer. In accordance with the design of the mask as a binary mask or phase mask, further transparent and/or opaque layers are applied to this carrier layer. These layers are preferably composed of silicon or molybdenum.
Masks of this type are transmission masks. As an alternative, the masks may also be formed as reflection masks, the mask in this case additionally having a non-transparent, reflective layer. As an alternative, the transparent carrier layer may be replaced by a non-transparent carrier layer.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a lithography method and mask for carrying out the method, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.